{"id":1179147,"date":"2026-07-20T06:41:51","date_gmt":"2026-07-20T13:41:51","guid":{"rendered":"https:\/\/research.codeghost.online\/en-us\/research\/publication\/omnilayout-a-schematic-coupled-multimodal-benchmark-for-constraint-aware-geometric-reasoning-in-pcb-layout\/"},"modified":"2026-07-22T05:05:59","modified_gmt":"2026-07-22T12:05:59","slug":"omnilayout-a-schematic-coupled-multimodal-benchmark-for-constraint-aware-geometric-reasoning-in-pcb-layout","status":"publish","type":"msr-research-item","link":"https:\/\/research.codeghost.online\/en-us\/research\/publication\/omnilayout-a-schematic-coupled-multimodal-benchmark-for-constraint-aware-geometric-reasoning-in-pcb-layout\/","title":{"rendered":"OmniLayout: A Schematic-Coupled Multimodal Benchmark for Constraint-Aware Geometric Reasoning in PCB Layout"},"content":{"rendered":"\n\n\n<p class=\"wp-block-paragraph\">Recent large language models (LLMs) have demonstrated remarkable progress in 3D spatial reasoning, spatial grounding, and fine-grained geometric understanding. However, their ability to reason about densely packed object placement under strict spatial and functional constraints remains largely unexplored, despite being a fundamental challenge in practical electronic design automation (EDA) workflows. To bridge this gap, we introduce OmniLayout, the first benchmark designed to evaluate LLMs on printed-circuit-board (PCB) layout placement reasoning under real-world geometric, routing, and connectivity constraints. OmniLayout contains 1,681 industrial-grade schematic-coupled PCB layouts and includes four tasks: (1) geometric reasoning for IC physical placement, with 77.24K placement instances constrained within PCB board boundaries; (2) routability-aware placement reasoning, generating physically valid component placements; (3) electrical functionality, preserving schematic-specified connectivity and electronic functional correctness; and (4) tool-augmented agentic reasoning for invoking external tools to accomplish tasks (1)-(3). Our results reveal substantial limitations of current LLMs in PCB layout placement, including weak geometric reasoning, poor routability optimization, and inconsistent preservation of electrical functionality.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Recent large language models (LLMs) have demonstrated remarkable progress in 3D spatial reasoning, spatial grounding, and fine-grained geometric understanding. However, their ability to reason about densely packed object placement under strict spatial and functional constraints remains largely unexplored, despite being a fundamental challenge in practical electronic design automation (EDA) workflows. To bridge this gap, we [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","msr-author-ordering":[{"type":"text","value":"Taiting Lu","user_id":0},{"type":"text","value":"Kaiyuan Lin","user_id":0},{"type":"text","value":"Mingjia Wang","user_id":0},{"type":"text","value":"Haolin Ye","user_id":0},{"type":"text","value":"Runze Liu","user_id":0},{"type":"text","value":"Yuxin Tian","user_id":0},{"type":"text","value":"V. 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